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sy89112u 2.5/3.3v low - jitter, low - skew 1:12 lvpecl fanout buffer with 2:1 input mux and internal termination precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com april 8 , 2014 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89112u is a low - jitter, low - skew, high - speed lvpecl 1:12 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. the input includes a 2:1 mux for clock switchover application. unlike other multiplexers, this input includes a unique isolation design to minimize channel - to - channel crosstalk. the sy89112u distributes clock frequencies from dc to >2ghz guaranteed over temperature and voltage. the sy89112u incorporates a synchronous output enable (en) so that the outputs will only be enabled/disabled when they are already in the low st ate. this reduces the chance of generating runt clock pulses. the sy89112u differential input includes micrels unique, patent - pending 3 - pin input termination architecture that directly interfaces to any differential signal (ac - or dc - coupled) as small a s 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. for ac - coupled input interface, an on - board output reference voltage (vref - ac) is provided to bias the center - tap (vt) pin. the outputs are 800mv, 100k - compat ible lvpecl with fast rise/fall times guaranteed to be less than 220ps. the sy89112u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temperature range of C 40c to +85c. the sy89112u is part of micrels high - speed, p recision edge ? product line. datasheets and support documentation are available on micrels web site at : www.micrel.com . features ? selects between 1 of 2 inputs, and provides 12 precision, low skew lvpecl output copie s ? guaranteed ac performance over temperature and voltage: ? dc to >2ghz throughput ? <550ps propagation delay clk - to - q ? <220ps rise/fall time ? <25ps output - to - output skew ? ultra - low jitter design: ? 50fs rms phase jitter (typ.) ? <0.7ps rms crosstalk induced jitter ? un ique, patent - pending input termination and vt pin accepts dc - coupled and ac - coupled differential inputs ? unique, patent - pending 2:1 input mux provides superior isolation to minimize channel - to - channel crosstalk ? 800mv, 100k lvpecl output swing ? power supply 2.5v + 5% or 3.3v + 10% ? ? industrial temperature range C 40c to +85c ? ? available in 44 - pin (7mm x 7mm) qfn package applications ? multi - processor server ? sonet/sdh clock/data distribution ? fibre channel distribution ? gigabit ethernet clock distribution
micrel, inc. sy89112u april 8 , 2014 2 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 functional block diagram
micrel, inc. sy89112u april 8 , 2014 3 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 ordering information part number ( 1 ) package type operating range package marking lead finish SY89112UMI qfn - 44 industrial sy89112u sn - pb SY89112UMItr ( 2 ) qfn - 44 industrial sy89112u sn - pb sy89112umy qfn - 44 industrial sy89112u with pb - free bar - line indicator matte - sn pb - free sy89112umytr ( 2 ) qfn - 44 industrial sy89112u with pb - free bar - line indicator matte - sn pb - free note s : 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 44 - pin qfn
micrel, inc. sy89112u april 8 , 2014 4 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 pin description pin number pin name pin function 2, 5 7, 10 clk0, /clk0 clk1, /clk1 differential inputs: these input pairs are the differential signal inputs to the device. inputs accept ac - or dc - coupled differential signals as small as 100mv. each pin of a pair internally terminates to a vt pin through 50 ? . note that these inputs will default to an indeterminate state if left open. please refer to the input interface appli cations section for more details. 3, 8 vt0, vt1 input termination center - tap: each side of the differential input pair terminates to a vt pin. the vt pins provide a center - tap to a termination network for maximum interface flexibility. see input interface applications section for more details. 4, 9 vref - ac0 vref - ac1 reference voltage: these outputs bias to v cc C 1.2v. they are used when ac coupling the inputs (clk, /clk). for ac - coupled applications, connect v ref - ac to the vt pin and by pass with a 0.01 ? f low esr capacitor to v cc . see input interface applications section for more details. maximum sink/source current is 1.5ma. due to the limited drive capability, each vref - ac pin is only intended to drive its respective vt pin. 44 clk _sel this single - ended ttl/cmos - compatible input selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull - up resistor and will default to a logic high state if left open. 12 en this single - ended ttl/cmos - compatibl e input functions as a synchronous output enable. the synchronous enable ensures that enable/disable will only occur when the outputs are in a logic low state. note that this input is internally connected to a 25k ? pull - up resistor and will default to logi c high state (enabled) if left open. 13,22,23,28, 33,34,43 vcc positive power supply. bypass with 0.1 ? f//0.01 ? f low esr capacitors and place as close to each vcc pin as possible. 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 q9, /q9 q10, /q10 q11, /q11 differential 100k lvpecl outputs: these lvpecl outputs are the precision, low skew copies of the inputs. please refer to the truth table below for details. unused output pairs may be left open. terminate with 50? to v cc C 2v. see lvpecl output interface applications section for more details. 1, 6, 11 gnd, exposed pad ground. gnd pins and exposed pad must both be connected to the most negative pote ntial of chip the ground. truth table en clk_sel q /q h l clk0 /clk0 h h clk1 /clk1 l x l ( 3 ) h ( 3 ) notes: 3. transition occurs on next negative transition of the non - inverted input.
micrel, inc. sy89112u april 8 , 2014 5 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 absolute maximum ratings ( 4 ) supply voltage (v cc ) ................................ .... ? 0.5v to ? 4.0v input voltage (v in ) ................................ .......... ? 0.5v to vcc lvpecl output current (i out ) continuous ................................ ................................ .. 50ma surge ................................ ................................ ......... 100ma termination current source or sink current on vt ................................ .. ? 100ma input current source or sink current on clk, /clk ........................ ? 50ma v ref - ac current source or sink current ................................ ................. ? 2ma lead temperature (soldering, 20sec) ...................... ? 260 ? c storage temperature (ts) ........................ ? 65 ? c to ? 150 ? c operating ratings ( 5 ) supply voltage (v cc ) ......................... ? 2.375v to ? 2.625v ? 3.0v to ? 3.6v ambient temperature (t a ) ....................... ? 40 ? c to ? 85 ? c package thermal resistance ( 6 ) qfn ( ? ja ) still - air ................................ ..................... 42 ? c/w qfn ( ? j b ) junction - to - board ................................ .... 20 ? c/w dc electrical characteristics ( 7 ) t a = C 40c to +85c, unless otherwise stated. symbol parameter condition min. typ. max. units v cc power supply 2.375 3.0 2.625 3.6 v v i cc power supply current no load, max. v cc 95 130 ma r in input resistance (in - to - vt) 45 50 55 ? diff_in differential input resistance (in - to - /in) 90 100 110 ? ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih C in input voltage swing (in, /in) see figure 1 0.1 1.7 v v diff_in differential input voltage swing |in C t_in in - to - vt (in, /in) 1.28 v v ref - ac output reference voltage v cc C cc C cc C notes: 4. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 5. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings 6. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ? j a and ? jb values are determined for a 4 - layer board in still - air, unless otherwise stated. 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established .
micrel, inc. sy89112u april 8 , 2014 6 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 lvpecl outputs dc electrical characteristics ( 7 ) v cc = +2.5v 5% or +3.3v 10%; t a = C 40c to +85c; r l = 50? to v cc C 2v, unless otherwise stated. symbol parameter condition min. typ. max. units v oh output high voltage ( q, /q) v cc C cc C ol output low voltage (q, /q) v cc C cc C out output voltage swing (q, /q) see figure 1a 550 800 mv v diff - out differential output voltage swing (q, /q) see figure 1b 1100 1600 mv lvttl/cmos dc electrical characteristics ( 7 ) v cc = +2.5v 5% or +3.3v 10%; t a = C 40c to +85c, unless otherwise stated. symbol parameter condition min. typ. max. units v ih input high voltage 2.0 v cc v v il input low voltage 0.8 v i ih input high current C il input low current C
micrel, inc. sy89112u april 8 , 2014 7 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 ac electrical characteristics ( 8 ) v cc = +2.5v 5% or +3.3v 10%; t a = C 40c to + 85c, r l = 50? to v cc C 2v, unless otherwise stated. symbol parameter condition min. typ. max. units f max maximum operating frequency v out 400mv pd propagation delay clk to q v in 100mv 300 400 550 ps propagation delay clk_sel to q 200 350 600 ps t pd tempco differential propagation delay temperature coefficient 150 fs/ o c t s set - up time en - to - clk note 9 0 ps t h hold time clk - to - en note 9 500 ps t skew output - to - output skew part - to - part skew note 10 note 11 25 200 ps t jitter rms phase jitter output = 622mhz, integration range: 12khz ? rms adjacent channel crosstalk - induced jitter note 12 0.7 ps (rms) t r, t f output rise/fall time (20% to 80%) at full output swing. 70 140 220 ps notes: 8. high - frequency ac - parameters are guaranteed by design and characterization. 9. set - up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for asynchrono us applications, set - up and hold do not apply. 10. output - to - output skew is measured between two different output s under identical input transitions. 11. part - to - part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. crosstalk is measured at the output while applying two simi lar differential clock frequencies that are asynchronous with respect to each other at the inputs.
micrel, inc. sy89112u april 8 , 2014 8 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 additive phase noise plot v cc = +3.3v, gnd = 0, r l = 50? to v cc C 2v, t a = 25c
micrel, inc. sy89112u april 8 , 2014 9 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 typical characteristics
micrel, inc. sy89112u april 8 , 2014 10 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 functional characteristics v cc = +3.3v, gnd = 0, v in = 100mv, r l = 50? to v cc C 2v, t a = 25c, unless otherwise stated.
micrel, inc. sy89112u april 8 , 2014 11 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 single - ended and differential swings figure 1 . single - ended voltage swing figure 2 . differential voltage swing timing diagram s figure 3 . t pd C differential in - to - differential out figure 4 . t pd C clk_sel - to - differential out figure 5 . t pd C set - up and hold time en - to - differential out
micrel, inc. sy89112u april 8 , 2014 12 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 input and output stages figure 6 . simplified differential input stage figure 7 . simplified lvpecl output stage input interface applications figure 8 . lvpecl interface (dc - coupled) figure 9 . lvpecl interface (ac - coupled) figure 10 . cml interface (dc - coupled) figure 11 . cml interface (ac - coupled) figure 12 . lvds interface
micrel, inc. sy89112u april 8 , 2014 13 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 lvpecl output interface applications lvpecl has high - input impedance, very - low output (open emitter) impedance, and small signal swing, which result in low emi. lvpecl is ideal for driving 50 ? and 100 ? controlled impedance transmission lines. there are several techniques for term inating the lvpecl output: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - coupled termination. unused output pairs may be left floating. however, single - ended outputs must be terminated or balanced. figure 13 . parallel thevenin - equivalent termination figure 14 . parallel termination (3 - resistor) related product and support documentation part number function datasheet link sy89113u 2.5v/3.3v low - jitter, low - skew, 1:12 lvds fanout buffer with 2:1 input mux and internal termination http://www.micrel.com/_pdf/hbw/sy89113u.pdf hbw solutions new products and applications http://www.micrel.com/index.php/en/products/clock - timing.html
micrel, inc. sy89112u april 8 , 2014 14 0 408 14 - 6.0 hbwhelp@micrel.com or (408) 955 - 1690 package information ( 13 ) 44 - pin qfn note: 13. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com . micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserv es the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in m icrels terms and conditions of sale for such products, micrel assumes no liability purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk a ? 20 14 micrel, incorporated.

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